The present invention relates to integrated circuits, and more specifically a hardware breakpoint unit for tracing bus events in a multi-bus system.
Advances in integrated circuit technology have made it possible to embed an entire system, including a processor core, a memory unit, a high performance bus, and a programmable logic, in a single semiconductor device. This type of programmable semiconductor device is commonly referred to as a system-on-chip (SoC), or a configurable system-on-chip (CSoC). The SoC provides many advantages over traditional processor-based designs. It is an attractive alternative to multi-chip designs because the integration of components into a single device increases overall speed while decreasing size. The SoC is also an attractive alternative to fully customized chips, such as an ASIC (application specific integrated circuit), because ASIC designs tend to have a significantly longer development time and larger development costs.
While the integration of components into a single chip provides many advantages, it often makes debugging chip firmware more difficult. Many of the methods and tools commonly used for debugging processor-based, embedded systems are less effective or simply do not work when the processor is deeply embedded in a chip. For example, logic analyzers and ICEs (in circuit emulators) are often ineffective tools for tracing bus events when the processor""s address and data busses are not available externally on the chip""s I/O (input/output) pins.
The lack of external access to address and data busses has led processor designers to develop on-chip debugging solutions. By adding debug logic to the processor core and making it accessible externally via a serial port, chip designers have made it possible to remotely control execution of a processor with minimal use of the target chip""s resources, such as ROM and I/O pins. However, this solution only allows tracing of a processor""s local bus.
New and complex SoCs are being developed with multiple processors and multiple busses. New SoC designs have a dedicated processor bus, connecting the processor core to on-chip memory, as well as a peripheral bus, connecting the application specific or programmable logic portion of the chip to the processor core. Prior art solutions do not address such multi-bus systems.
A breakpoint unit for a configurable system-on-chip with multiple busses is disclosed. The breakpoint unit is coupled to the busses and able to break on a specified bus event on a selected bus.